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SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
April 2009
SG6742HL/HR Highly Integrated Green-Mode PWM Controller
Features
High-Voltage Startup Low Operating Current: 2.7mA Linearly Decreasing PWM Frequency to 22KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 100KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Internal Open-Loop Protection GATE Output Maximum Voltage Clamp: 18V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OVP, OTP) Internal-Sense, Short-Circuit Protection Built-in 6ms Soft-Start Function Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis
Description
The highly integrated SG6742HL/HR PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is eliminated. To further reduce power consumption, SG6742HL/HR is manufactured using the BiCMOS process, which allows an operating current of 2.7mA. SG6742HL/HR integrates a frequency-hopping function internally that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary, internal line compensation ensures constant output power limit over a wide AC input voltage range, from 90VAC to 264VAC. SG6742HL/HR provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until VDD drops below the UVLO lower limit, when the controller starts up again. As long as VDD exceeds ~25V, the internal OVP circuit is triggered. SG6742HL/HR is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS
Ordering Information
Part Number
SG6742HLSY SG6742HRSY
Operating Temperature Range
-40 to +105C -40 to +105C
OLP Function
Latch Restart
Package
8-Lead Small Outline Package (SOP) 8-Lead Small Outline Package (SOP)
Eco Status
Green Green
Packing Method
Tape & Reel Tape & Reel
For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
SG6742HL
SG6742HR
Figure 2. Functional Block Diagram
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4 www.fairchildsemi.com 2
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Marking Information
F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (S=SOP) P - Y: Green Package M - Manufacture Flow Code
ZXYTT 6742HR TPM
ZXYTT 6742HL TPM
Figure 3. Top Mark
Pin Configuration
SOP-8 GND FB NC HV 1 2 3 4 8 7 6 5 GATE VDD SENSE RT
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
GND FB NC HV RT SENSE VDD GATE
Description
Ground. The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin. No connection. For startup, this pin is pulled high to the line input or bulk capacitor via resistors. For over-temperature protection, an external NTC thermistor is connected from this pin to the GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM output is latched. Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. The totem-pole output driver. Soft driving waveform is implemented for improved EMI.
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com 3
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD VFB VSENSE VRT VHV PD JA TJ TSTG TL DC Supply Voltage
(1, 2)
Parameter
FB Pin Input Voltage SENSE Pin Input Voltage RT Pin Input Voltage HV Pin Input Voltage Power Dissipation (TA50C) Thermal Resistance (Junction-to-Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model, JEDEC:JESD22-A114 Charged Device Model, JEDEC:JESD22-C101 All pins except HV pin All pins except HV pin
Min.
-0.3 -0.3 -0.3
Max.
30 7.0 7.0 7.0 500 400 141
Unit
V V V V V mW C/W C C C
-40 -55
+125 +150 +260 4.0
ESD
kV 1.5
Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com 4
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25C unless otherwise noted.
Symbol VDD Section
VOP VDD-ON VDD-OFF IDD-ST IDD-OP IDD-OLP VTH-OLP VDD-OVP tD-VDDOVP
Parameter
Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage Startup Current Operating Supply Current Internal Sink Current IDD-OLP off Voltage VDD Over-Voltage Protection VDD Over-Voltage Protection Debounce Time
Conditions
Min.
Typ.
Max.
22
Units
V V V A mA A V V s
14.5 8.5 VDD-ON - 0.16V VDD=15V, GATE Open VTH-OLP+0.1V 30 6.5 24 75
15.5 9.5 2.7 60 7.5 25 125
16.5 10.5 30 3.7 90 8.0 26 200
HV Section
IHV IHV-LC Supply Current from HV Pin Leakage Current After Startup VAC=90V (VDC=120V), VDD=0V HV=500V, VDD=VDDOFF+1V 1.75 2.30 1 3.35 20 mA
A
Oscillator Section
fOSC tHOP fOSC-G fDV fDT Frequency in Normal Mode Hopping Period Green-Mode Frequency Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation VDD=11V to 22V TA=-40 to 105C Center Frequency Hopping Range 90 4.2 4.9 18 100 4.7 5.6 22 110 5.2 6.3 25 5 5 KHz ms KHz % %
Continued on the following page...
PWM Frequency fOSC
fOSC-G
VFB-ZDC VFB-G
VFB-N
VFB
Figure 5. VFB vs. PWM Frequency
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com 5
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25C unless otherwise noted.
Symbol
Feedback Input Section AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N VFB-G VFB-ZDC ZSENSE VSTHFL VSTHVA tPD tLEB VS-SCP tD-SSCP tSS DCYMAX VGATE-L VGATE-H tr tf IGATESOURCE
Parameter
Input Voltage to Current-Sense Attenuation Input Impedance Output High Voltage FB Open-Loop Trigger Level Delay Time of FB Pin Open-loop Protection Green-Mode Entry FB Voltage Green-Mode Ending FB Voltage Zero Duty-Cycle Input Voltage Input Impedance Current Limit Flatten Threshold Voltage Current Limit Valley Threshold Voltage Delay to Output Leading-Edge Blanking Time
Conditions
Min.
1/4.15 4
Typ.
1/4.00 5.2
Max. Units
1/3.85 7 V/V k V 5.0 62 3.5 V ms V V V K 1.03 0.33 200 180 0.20 200 7 70 1.5 V V ns ns V s ms % V V ns ns mA mA 18 V
FB Pin Open 4.6 50 3.1
4.8 56 3.3 VFB-N0.5
1.6 12 Duty cycle=45% VSTHFL-VSTHVA 0.97 0.27 100 0.10 100 5 60 VDD=15V, IO=50mA VDD=12V, IO=50mA VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=15V, GATE=6V VDD=15V, GATE=1V VDD=22V 8 150 30 250 300 250 50 350 90 1.00 0.30 100 140 0.15 150 6 65
Current-Sense Section
Threshold Voltage for SENSE Short-Circuit Protection Delay Time for SENSE Short-Circuit Protection Period During Soft-Startup Time Maximum Duty Cycle Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Gate Source Current VSENSE<0.15V Startup Time
GATE Section
IGATE-SINK Gate Sink Current VGATECLAMP
Gate Output Clamping Voltage
RT Section RRT VRTTH1 VRTTH2 tD-OTP1 tD-OTP2 TOTP TRestart Internal Resistor from RT Pin Over-Temperature Protection Threshold Voltage 0.7V VRT 1.05V, After 12ms Latch Off VRT 0.7V, After 100s Latch Off VRTTH2 VRT VRTTH1 VRT< VRTTH2 10.08 1.015 0.65 16 90 10.50 1.050 0.70 20 130 +135 TOTP-25 10.92 1.085 0.75 24 170 K V V ms s C C
Over-Temperature Latch-off Debounce
Over-Temperature Protection Section (OTP) Protection Junction Temperature Restart Junction Temperature
(4) (3)
Notes: 3. When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated.
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4 www.fairchildsemi.com 6
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
25 5
20
4
IDD_ST (A)
15
IDD-OP (mA)
-30 -15 0 25 50 75 85 100 125
3
10
2
5
1
0 -40
0 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 6. Startup Current (IDD-ST) vs. Temperature
18
Figure 7. Operation Supply Current (IDD-OP) vs. Temperature
12
17
11
VDD-ON (V)
16
VDD-OFF (V)
-30 -15 0 25 50 75 85 100 125
10
15
9
14
8
13 -40
7 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 8. Start Threshold Voltage (VDD-ON) vs. Temperature
5
Figure 9. Minimum Operating Voltage (VDD-OFF) vs. Temperature
10
4
8
2
IHV-LC (A)
-30 -15 0 25 50 75 85 100 125
IHV (mA)
3
6
4
1
2
0 -40
0 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 10. Supply Current Drawn from HV Pin (IHV) vs. Temperature
105
Figure 11. HV Pin Leakage Current after Startup (IHV-LC) vs. Temperature
70
103
68
101
DCY MAX (%)
-30 -15 0 25 50 75 85 100 125
FOSC (kHz)
66
99
64
97
62
95 -40
60 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 12. Frequency in Normal Mode (fOSC) vs. Temperature
Figure 13. Maximum Duty Cycle (DCYMAX) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
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SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
7 62 60 6 58
VFB-OLP (V)
5
tD-OLP (ms)
56 54
4 52 3 -40 50 -40
-30
-15
0
25
50
75
85
100
125
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 14. FB Open-Loop Trigger Level (VFB-OLP) vs. Temperature
0.15
Figure 15. Delay Time of FB Pin Open-Loop Protection (tD-OLP) vs. Temperature
100
0.145
99
VS-SCP (V)
0.14
IRT (A)
-30 -15 0 25 50 75 85 100 125
98
0.135
97
0.13 -40
96 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 16. Threshold Voltage for SENSE Short-Circuit Protection (VS-SCP) vs. Temperature
1.2
Figure 17. Output Current from RT Pin (IRT) vs. Temperature
0.9
1.1
0.8
VRTTH1 (V)
1
VRTTH2 (V)
-30 -15 0 25 50 75 85 100 125
0.7
0.9
0.6
0.8 -40
0.5 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 18. Over-Temperature Protection Threshold Voltage (VRTTH1) vs. Temperature
28
Figure 19. Over-Temperature Protection Threshold Voltage (VRTTH2) vs. Temperature
27
VDD-OVP (V)
26
25
24
23 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Figure 20. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4 www.fairchildsemi.com 8
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, RHV, (1N4007 / 100K recommended). Typical startup current drawn from pin HV is 2.3mA and charges the hold-up capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the SG6742HL/HR to keep the VDD before the auxiliary winding of the main transformer to provide the operating current.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the inrush current at startup. The built-in 6ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot.
Operating Current
Operating current is around 2.7mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG6742HL/HR inserts a synchronized positive-going ramp at every switching cycle.
Green-Mode Operation
The proprietary green-mode function provides an offtime modulation to reduce the switching frequency in the light-load and no-load conditions. The on time is limited for better abnormal or brownout protection. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz.
Constant Output Power Limit
When the SENSE voltage, across the sense resistor RS, reaches the threshold voltage, around 1V, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD * VIN / LP. Since the delay is nearly constant regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current sense signal and VFB, the feedback voltage. When the voltage on SENSE pin reaches around VCOMP=(VFB-0.6)/4, a switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. If the VDD voltage is over the over-voltage protection voltage (VDD-OVP) and lasts for tD-VDDOVP, the PWM pulses are disabled until the VDD voltage drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 15.5V and 9.5V. During startup, the hold-up capacitor must be charged to 15.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 9.5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup.
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4 www.fairchildsemi.com 9
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
Thermal Protection
An NTC thermistor, RNTC, in series with a resistor RA, can be connected from the RT pin to ground. A constant current IRT is output from the RT pin. The voltage on the RT pin can be expressed as VRT = IRT * (RNTC + RA), where IRT is 100A. At high ambient temperatures, RNTC is smaller, such that VRT decreases. When VRT is less than 1.05V (VRTTH1), the PWM turns off after 20ms (tD-OTP1). If VRT is less than 0.7V (VRTTH2), PWM turns off immediately after 130s (tD-OTP2).
Noise Immunity
Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG6742HL/HR, and increasing the power MOS gate resistance improve performance.
Limited Power Control
The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, VDD begins decreasing. When VDD goes below the turn-off threshold (~9.5V) the controller is totally shut down. VDD is charged up to the turn-on threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. When VRT is less than 1.05V (VRTTH1), the PWM is turned off after 20ms (tD-OTP1). If VRT is less than 0.7V (VRTTH2), PWM is turned off immediately after 130s (tD-OTP2).
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com 10
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Applications Information
F1 2 4 2 CN1 1 2 3 CN1 1 3 L1 T1 4 VZ1 C1 C2 1 3 4
2
BD1 1 1 2 4 5 6 2 1 T2 8 3 + 3 C4 2 C3 D4 C5 R1
R2
C6
2 Q1 1 2 + C7 1 1 VO+ 2 2 2 L3 + C8 1 3 D1 4 1
L2
VO+
1
1
D2
3
7
2
VO2 R3 2 R4 1 3 D3 1 2 + U1 1 2 C12 3 4 SG6742MR 8 7 6 5 R6 C10 R5 1 C9 GND GATE FB NC HV VDD SENSE RT 2 R7 THER1 R8 VO+ 4 U2 1 R9 R10 3 2 K C11 R U3 A R11 Q2
Figure 21. 60W Flyback 12V/5A Application Circuit
BOM
Designator
BD1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 F1 L1 L2
Part Type
BD 4A/600V XC 0.68F/300V XC 0.1F/300V YC 2200pF/Y1 EC 120F/400V CC 0.01F/500V CC 1000pF/100V EC 1000F/25V EC 470F/25V EC 22F/50V CC 47pF/50V CC 2200pF/50V CC 0.01F/50V Zener Diode 15V 1/2W (option) BYV95C FR103 1N4007 FUSE 4A/250V Inductor (900H) Inductor (2H) L3 Q1 Q2 R1 R2 R3 R4 R5
Designator
Part Type
Inductor (900H) STP20-100CT MOS 7A/600V R 100K 1/2W R 47 1/4W R 100K 1/2W R 4.7 1/8W R 100 1/8W R 4.7K 1/8W R 0.3 2W R 680 1/8W R 150K 1/8W R 39K 1/8W Thermistor TTC104 10mH 255H(PQ2620) IC SG6742 IC PC817 IC TL431 VZ 9G
R6, R9 R7 R8 R10 R11 THER1 T1 T2 U1 U2 U3 VZ1
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
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SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 22. 8-Pin SOP-8 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com 12
SG6742HL/HR -- Highly Integrated Green-Mode PWM Controller
(c) 2008 Fairchild Semiconductor Corporation SG6742HL/HR * Rev. 1.0.4
www.fairchildsemi.com 13

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